The present invention relates to a method of fabricating a non-volatile memory device, and more particularly, to a method of fabricating a non-volatile memory device which employs a high-k dielectric layer as an intergate insulation layer.
Memory devices used to store data may be classified into a volatile memory device and a non-volatile memory device depending on ability whether it can maintain the data even when power supply is cut off. While the volatile memory device loses the stored data when the power supply is cut off, the non-volatile memory device maintains the stored data even when the power supply is cut off. Therefore, the non-volatile memory device is widely used where the power supply is always unavailable or interrupted sometimes or use of lower power is required such as a mobile telephone system, a memory card for storing music/movie data and other application devices.
FIG. 1 is a cross-sectional view illustrating a conventional non-volatile memory device having a floating gate stack structure. Referring to FIG. 1, on a semiconductor substrate 100 having an active region 104 defined by an isolation layer 102 is disposed a tunnel insulation layer pattern 110, on which a plurality of floating gate electrode layer patterns 120 are disposed apart from each other. An intergate insulation layer 130 is disposed over the exposed surface of the isolation layer 102 and the floating gate electrode layer patterns. A control gate electrode layer 140 is disposed over the intergate insulation layer 130. The tunnel insulation layer 110 is made of an oxide layer and the intergate insulation layer 130 is made of an oxide layer/nitride layer/oxide layer (ONO) structure. Also, the floating gate electrode layer pattern 120 and the control gate electrode 140 are made of a polysilicon layer.
However, as an integration degree of the non-volatile memory device is increased, a distance between the floating gate electrode layer patterns 120 is more and more decreased. Accordingly, a space between the floating gate electrode layer patterns 120 in which the control gate electrode layer 140 is inserted becomes insufficient and generation of an interference between the floating gate electrode layer patterns 120 by a parasitic capacitance 150 is getting serious. Therefore, in order to restrict the problem, there have been recently tried efforts of reducing a thickness of the intergate insulation layer 130 together with employment of a planar structure in which the intergate insulation layer 130 is excluded from side faces of the floating gate electrode layer patterns 120. However, it is known that it is not easy to reduce the thickness of an effective oxide layer to below a certain thickness with the currently used intergate insulation layer 130 with the ONO structure. For example, in order to maintain a coupling ratio above 0.5 while employing the planar structure, the thickness of the effective oxide layer be maintained below 80 Å. However, it is hard to actually apply the intergate insulation layer 130 of the ONO structure having the thickness of the effective oxide layer of below 80 Å since leakage current is rapidly increased.
Accordingly, there has been studied a method of forming the intergate insulation layer 130 using a high-k dielectric layer having a high dielectric constant instead of the ONO structure. However, the use of the high-k dielectric layer as the intergate insulation layer 130 may cause the following problems. First, upon deposition of the high-k dielectric layer or subsequent thermal process, the high-k dielectric layer and the floating gate electrode layer pattern 120 are react to form a silicon oxide (SiO2) layer. This silicon oxide layer may rather increase the thickness of the effective oxide layer of the intergate insulation layer 130. Second, crystallization of the high-k dielectric layer itself by the subsequent thermal process occurs and this may deteriorate the leakage current properties. Third, phase separation of the high-k dielectric layer by the subsequent thermal process occurs and impurities are diffused into the high-k dielectric layer upon formation of the control gate layer electrode 140, which may lead to deterioration of the leakage current properties.